Publications | THInK Team

Patents

S. S. Iyer, K. K. Thankappan, and B. Vaisband, "On-chip Electrostatic Discharge Sensor," United States Patent No. 2022/0392893 A1, December 8, 2022.
B. Vaisband, A. Bajwa, and S. S. Iyer “Power Distribution within Silicon Interconnect Fabric,” United States Patent No. 2021/0225749 A1, July 22, 2021.
Boris Vaisband, S. S. Iyer, A. Bajwa, A. Dasgupta, and A. Alam “Network on Interconnect Fabric and Integrated Antenna,” United States Patent No. 2020/0403293, December 24, 2020.

Book Chapters

S. S. Iyer and B. Vaisband, “Heterogeneous Integration at Scale,” Advances in Semiconductor Technologies, A. Chen, Wiley/IEEE, 2022.
B. Vaisband and E. G. Friedman, “Substrate Noise Coupling in Heterogeneous 3-D ICs,” Three-Dimensional Integrated Circuit Design, 2nd Edition, V. F. Pavlidis and E. G. Friedman, Morgan Kaufmann, 2017.
B. Vaisband and E. G. Friedman, “3-D IC Floorplanning Based on Thermal Interactions,” Noise Coupling in System-on-Chip, T. Noulis (Ed.), CRC Press, 2017.
B. Vaisband and E. G. Friedman, “TSV to Substrate Noise Coupling in Heterogeneous 3-D ICs,” Noise Coupling in System-on-Chip, T. Noulis (Ed.), CRC Press, 2017.

Journal Papers

M. Karimi, A. Saeed Monir, R. Mohammadrezaee, and B. Vaisband, "CTT-Based Scalable Neuromorphic Architecture," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 13, No. 1, pp. 96-107, March 2023, JETCAS Spotlight Paper.
Y. Safari and B. Vaisband, “A Robust Integrated Power Delivery Methodology for 3-D ICs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 31, No. 3, pp. 287-295, March 2023.
M. Karimi, M. Ali, A. Hassan, R. Bostani, B. Vaisband, M. Sawan, and B. Gosselin, “A 7.6 ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source,” IEEE Access, Vol. 10, pp. 132432-132447, December 2022.
K. Kalappurakal Thankappan, B. Vaisband, K. Sahoo, and S. S. Iyer, “An On-Chip ESD Sensor for Use in Advanced Packaging,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 12, No. 7, pp. 1051-1062, July 2022.
Y. Safari and B. Vaisband, “Wafer-Scale Integration,” Wiley Encyclopedia of Electrical and Electronics Engineering, pp. 1-10, February 2022.
Y. Zhu, C. W. Tan, S. L. Chua, Y. D. Lim, B. Vaisband, B. K. Tay, E. G. Friedman, C. S. Tan, “Assembly Process and Electrical Property of Top-Transferred Graphene on Carbon Nanotubes for Carbon-Based Three-Dimensional Interconnects,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 10, No. 3, pp. 516-524, March 2020.
K. Xu, B. Vaisband, G. Sizikov, X. Li, and E. G. Friedman, “EMI Suppression with Distributed LLC Resonant Converter for High Voltage VR-on-Package,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 10, No. 2, pp. 263-271, February 2020.
S. S. Iyer, S. Jangam, and B. Vaisband, “Silicon Interconnect Fabric: A Versatile Heterogeneous Integration Platform for AI Systems,” IBM Journal of Research and Development, Vol. 63, No. 6, pp. 5:1-5:16, November/December 2019.
K. Xu, B. Vaisband, G. Sizikov, X. Li, and E. G. Friedman, “Power Noise and Near Field EMI of High Current System-in-Package with VR Top and Bottom Placement,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 9, No. 4, pp. 712-718, April 2019.
B. Vaisband and E. G. Friedman, “Heterogeneous 3-D ICs as a Platform for Hybrid Energy Harvesting in IoT Systems,” Future Generation Computer Systems, Vol. 87, pp. 152-158, October 2018.
B. Vaisband, A. Maurice, C. W. Tan, B. K. Tay, and E. G. Friedman, “Electrical and Thermal Models of the Interface between CNT TSVs and Graphite Interconnects,” IEEE Transactions on Electron Devices, Vol. 65, No. 5, pp. 1880-1886, May 2018.
B. Vaisband and E. G. Friedman, “Hexagonal TSV Bundle Topology for 3-D ICs,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 1, pp. 11-15, January 2017.
B. Vaisband and E. G. Friedman, “Noise Coupling Models in Heterogeneous 3-D ICs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 8, pp. 2778-2786, August 2016.
I. Savidis, B. Vaisband, and E. G. Friedman, “Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2077-2089, October 2015.

Conference Papers

F. R. Amik, Y. Safari, Z. Zhang, and B. Vaisband, “Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model,” Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2025. (Accepted)
Y. Safari, Y. Zhao, and B. Vaisband, “Trench-Based Fully Integrated Capacitors for Power Delivery in Heterogeneous Integration Platforms,” Proceedings of the IEEE Electronics System-Integration Technology Conference (ESTC), pp. 1-8, September 2024.
Y. Safari, Y. Zhao, and B. Vaisband, “Co-DTC: Concentric Trench-Based Integrated Capacitors for Advanced Chiplet-Based Platforms,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, June 2024.
Y. Safari, R. Mohammadrezaee, D. Al Saleh, and B. Vaisband, “Hybrid Interconnect Infrastructure for Inter-Chiplet Communication in Wafer-Scale Systems,” Proceedings of the IEEE Electronic Components and Technology Conference (ECTC), pp. 2229-2236, May 2024.
D. Al Saleh, Y. Safari, F. Rahman Amik, B. Vaisband, “P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICs,” Proceedings of the IEEE International System-on-Chip Conference (SoCC), pp. 1-6, September 2023.
Y. Safari, P. Aghanoury, S. S. Iyer, N. Sehatbakhsh, and B. Vaisband, "Hybrid Obfuscation of Chiplet-Based Systems," Proceedings of the IEEE/ACM Design Automation Conference, pp. 1-6, July 2023.
S. Dayo, A. Saeed Monir, M. Karimi, and B. Vaisband, "Statistical Weight Refresh System for CTT-Based Synaptic Arrays," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 213-214, June 2023, Best Poster Award.
O. Gumus, M. Karimi, and B. Vaisband, "Digital LIF Neuron for CTT-Based Neuromorphic Systems," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 267-272, June 2023.
Y. Safari, A. Corbier, D. Al Saleh, and B. Vaisband, “ARTSim: A Robust Thermal Simulator for Heterogeneous Integration Platforms,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 1187-1193, 2023.
Y. Safari, A. Kroon, and B. Vaisband, “Power Delivery for Ultra-Large-Scale Applications on Si-IF,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1605-1609, June 2022.
Y. Safari, Y.-T. Yang, S. S. Iyer, T. Nakatani, N. Levine, and B. Vaisband, “Split-Fabric: A Novel Wafer-Scale Hardware Obfuscation Methodology using Silicon Interconnect Fabric,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 660-667, June 2022.
Y. Safari and B. Vaisband, “Integrated Power Delivery Methodology for 3D ICs,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 114-119, April 2022.
Y. Safari and B. Vaisband, “Power Delivery for Silicon Interconnect Fabric,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2021.
B. Vaisband, A. Maurice, C. W. Tan, B. K. Tay, and E. G. Friedman, “Multi-Bit CNT TSV for 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1-5, October 2020.
B. Vaisband and S. S. Iyer, “Global and Semi-Global Communication on Silicon Interconnect Fabric,” Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip, pp. 15:1-15:5, October 2019.
B. Vaisband and S. S. Iyer, “Communication Considerations for Silicon Interconnect Fabric”, Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 1-6, June 2019.
S. S. Iyer, S. Jangam, and B. Vaisband, “From Homogeneous SoCs to Heterogeneous SoWs,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2019.
K. Kalappurakal Thankappan, A. Bajwa, S. Jangam, B. Vaisband, and S. S. Iyer, “Reliability Evaluation of Silicon Interconnect Fabric Technology,” Proceedings of the IEEE International Reliability Physics Symposium, April 2019.
K. Kalappurakal Thankappan, B. Vaisband, and S. S. Iyer, “On-Chip ESD Monitor,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 2225-2233, May 2019.
E. Sorensen, B. Vaisband, S. Jangam, T. Shirley, and S. S. Iyer, “Integration and Characterization of InP Dies on Silicon Interconnect Fabric,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 543-549, May 2019.
P. Ambhore, U. Mogera, B. Vaisband, M. Goorsky, and S. S. Iyer, “PowerTherm Attach Process for Power Delivery and Heat Extraction in the Silicon-Interconnect Fabric using Thermocompression Bonding,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 1605-1610, May 2019.
M.-H. Liu, B. Vaisband, A. Hanna, Y. Luo, Z. Wan, and S. S. Iyer, “Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 579-586, May 2019.
U. Shah, U. Mogera, P. Ambore, B. Vaisband, S. S. Iyer, and T. S. Fisher, “Dynamic Thermal Management for Silicon Interconnect Fabric using Flash Cooling,” Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, pp. 1228-1233, May 2019.
A. Bajwa, S. Jangam, S. Pal, B. Vaisband, R. Irwin, M. Goorsky, and S. S. Iyer, “Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly,” Proceedings of the IEEE Electronic Components and Technology Conference (ECTC), pp. 1926-1930, May 2018.
B. Vaisband, A. Bajwa, and S. S. Iyer, “Network on Interconnect Fabric,” Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 138-143, March 2018.
K. Xu, B. Vaisband, G. Sizikov, X. Li, and E. G. Friedman, “Distributed Sinusoidal Resonant Converter with High Step-Down Ratio,” Proceedings of the IEEE International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 1-3, October 2017.
B. Vaisband and E. G. Friedman, “Hybrid Energy Harvesting in 3-D IC IoT Devices,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2017.
B. Vaisband and E. G. Friedman, “3-D ICs as a Platform for IoT Devices,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2017.
B. Vaisband and E. G. Friedman, “Noise Coupling in TSV-Based Heterogeneous 3-D ICs,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2017.
B. Vaisband and E. G. Friedman, “Layer Ordering to Minimize TSVs in Heterogeneous 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1926-1929, May 2016.
B. Vaisband and E. G. Friedman, “3-D Floorplanning Algorithm to Minimize Thermal Interactions,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2133-2136, May 2015.
B. Vaisband, I. Savidis, and E. G. Friedman, “Thermal Conduction Path Analysis in 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 594-597, June 2014.
B. Vaisband and E. G. Friedman, “Analysis of Thermal Paths in 3-D Structures,” Proceedings of the 37th Annual IEEE EDS/CAS Activities in Western New York Conference, p. 6, November 2013.

Patents

S. S. Iyer, K. K. Thankappan, and B. Vaisband, "On-chip Electrostatic Discharge Sensor," United States Patent No. 2022/0392893 A1, December 8, 2022.

B. Vaisband, A. Bajwa, and S. S. Iyer “Power Distribution within Silicon Interconnect Fabric,” United States Patent No. 2021/0225749 A1, July 22, 2021.

Boris Vaisband, S. S. Iyer, A. Bajwa, A. Dasgupta, and A. Alam “Network on Interconnect Fabric and Integrated Antenna,” United States Patent No. 2020/0403293, December 24, 2020.

Book Chapters

S. S. Iyer and B. Vaisband, “Heterogeneous Integration at Scale,” Advances in Semiconductor Technologies, A. Chen, Wiley/IEEE, 2022.

B. Vaisband and E. G. Friedman, “Substrate Noise Coupling in Heterogeneous 3-D ICs,” Three-Dimensional Integrated Circuit Design, 2nd Edition, V. F. Pavlidis and E. G. Friedman, Morgan Kaufmann, 2017.

B. Vaisband and E. G. Friedman, “3-D IC Floorplanning Based on Thermal Interactions,” Noise Coupling in System-on-Chip, T. Noulis (Ed.), CRC Press, 2017.

B. Vaisband and E. G. Friedman, “TSV to Substrate Noise Coupling in Heterogeneous 3-D ICs,” Noise Coupling in System-on-Chip, T. Noulis (Ed.), CRC Press, 2017.

Journal Papers

M. Karimi, A. Saeed Monir, R. Mohammadrezaee, and B. Vaisband, "CTT-Based Scalable Neuromorphic Architecture," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 13, No. 1, pp. 96-107, March 2023, JETCAS Spotlight Paper.

Y. Safari and B. Vaisband, “A Robust Integrated Power Delivery Methodology for 3-D ICs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 31, No. 3, pp. 287-295, March 2023.

M. Karimi, M. Ali, A. Hassan, R. Bostani, B. Vaisband, M. Sawan, and B. Gosselin, “A 7.6 ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source,” IEEE Access, Vol. 10, pp. 132432-132447, December 2022.

K. Kalappurakal Thankappan, B. Vaisband, K. Sahoo, and S. S. Iyer, “An On-Chip ESD Sensor for Use in Advanced Packaging,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 12, No. 7, pp. 1051-1062, July 2022.

Y. Safari and B. Vaisband, “Wafer-Scale Integration,” Wiley Encyclopedia of Electrical and Electronics Engineering, pp. 1-10, February 2022.

K. Xu, B. Vaisband, G. Sizikov, X. Li, and E. G. Friedman, “EMI Suppression with Distributed LLC Resonant Converter for High Voltage VR-on-Package,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 10, No. 2, pp. 263-271, February 2020.

S. S. Iyer, S. Jangam, and B. Vaisband, “Silicon Interconnect Fabric: A Versatile Heterogeneous Integration Platform for AI Systems,” IBM Journal of Research and Development, Vol. 63, No. 6, pp. 5:1-5:16, November/December 2019.

K. Xu, B. Vaisband, G. Sizikov, X. Li, and E. G. Friedman, “Power Noise and Near Field EMI of High Current System-in-Package with VR Top and Bottom Placement,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 9, No. 4, pp. 712-718, April 2019.

B. Vaisband and E. G. Friedman, “Heterogeneous 3-D ICs as a Platform for Hybrid Energy Harvesting in IoT Systems,” Future Generation Computer Systems, Vol. 87, pp. 152-158, October 2018.

B. Vaisband, A. Maurice, C. W. Tan, B. K. Tay, and E. G. Friedman, “Electrical and Thermal Models of the Interface between CNT TSVs and Graphite Interconnects,” IEEE Transactions on Electron Devices, Vol. 65, No. 5, pp. 1880-1886, May 2018.

B. Vaisband and E. G. Friedman, “Hexagonal TSV Bundle Topology for 3-D ICs,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 1, pp. 11-15, January 2017.

B. Vaisband and E. G. Friedman, “Noise Coupling Models in Heterogeneous 3-D ICs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, No. 8, pp. 2778-2786, August 2016.

I. Savidis, B. Vaisband, and E. G. Friedman, “Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2077-2089, October 2015.

Conference Papers

F. R. Amik, Y. Safari, Z. Zhang, and B. Vaisband, “Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model,” Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), January 2025. (Accepted)

Y. Safari, Y. Zhao, and B. Vaisband, “Trench-Based Fully Integrated Capacitors for Power Delivery in Heterogeneous Integration Platforms,” Proceedings of the IEEE Electronics System-Integration Technology Conference (ESTC), pp. 1-8, September 2024.

Y. Safari, Y. Zhao, and B. Vaisband, “Co-DTC: Concentric Trench-Based Integrated Capacitors for Advanced Chiplet-Based Platforms,” Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 1-6, June 2024.

Y. Safari, R. Mohammadrezaee, D. Al Saleh, and B. Vaisband, “Hybrid Interconnect Infrastructure for Inter-Chiplet Communication in Wafer-Scale Systems,” Proceedings of the IEEE Electronic Components and Technology Conference (ECTC), pp. 2229-2236, May 2024.

D. Al Saleh, Y. Safari, F. Rahman Amik, B. Vaisband, “P* Admissible Thermal-Aware Matrix Floorplanner for 3D ICs,” Proceedings of the IEEE International System-on-Chip Conference (SoCC), pp. 1-6, September 2023.

Y. Safari, P. Aghanoury, S. S. Iyer, N. Sehatbakhsh, and B. Vaisband, "Hybrid Obfuscation of Chiplet-Based Systems," Proceedings of the IEEE/ACM Design Automation Conference, pp. 1-6, July 2023.

S. Dayo, A. Saeed Monir, M. Karimi, and B. Vaisband, "Statistical Weight Refresh System for CTT-Based Synaptic Arrays," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 213-214, June 2023, Best Poster Award.

O. Gumus, M. Karimi, and B. Vaisband, "Digital LIF Neuron for CTT-Based Neuromorphic Systems," Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI, pp. 267-272, June 2023.

Y. Safari, A. Corbier, D. Al Saleh, and B. Vaisband, “ARTSim: A Robust Thermal Simulator for Heterogeneous Integration Platforms,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 1187-1193, 2023.

Y. Safari, A. Kroon, and B. Vaisband, “Power Delivery for Ultra-Large-Scale Applications on Si-IF,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1605-1609, June 2022.

Y. Safari, Y.-T. Yang, S. S. Iyer, T. Nakatani, N. Levine, and B. Vaisband, “Split-Fabric: A Novel Wafer-Scale Hardware Obfuscation Methodology using Silicon Interconnect Fabric,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 660-667, June 2022.

Y. Safari and B. Vaisband, “Integrated Power Delivery Methodology for 3D ICs,” Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 114-119, April 2022.

Y. Safari and B. Vaisband, “Power Delivery for Silicon Interconnect Fabric,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1-5, May 2021.

B. Vaisband, A. Maurice, C. W. Tan, B. K. Tay, and E. G. Friedman, “Multi-Bit CNT TSV for 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1-5, October 2020.

B. Vaisband and S. S. Iyer, “Global and Semi-Global Communication on Silicon Interconnect Fabric,” Proceedings of the IEEE/ACM International Symposium on Networks-on-Chip, pp. 15:1-15:5, October 2019.

B. Vaisband and S. S. Iyer, “Communication Considerations for Silicon Interconnect Fabric”, Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 1-6, June 2019.

S. S. Iyer, S. Jangam, and B. Vaisband, “From Homogeneous SoCs to Heterogeneous SoWs,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2019.

K. Kalappurakal Thankappan, A. Bajwa, S. Jangam, B. Vaisband, and S. S. Iyer, “Reliability Evaluation of Silicon Interconnect Fabric Technology,” Proceedings of the IEEE International Reliability Physics Symposium, April 2019.

K. Kalappurakal Thankappan, B. Vaisband, and S. S. Iyer, “On-Chip ESD Monitor,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 2225-2233, May 2019.

E. Sorensen, B. Vaisband, S. Jangam, T. Shirley, and S. S. Iyer, “Integration and Characterization of InP Dies on Silicon Interconnect Fabric,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 543-549, May 2019.

M.-H. Liu, B. Vaisband, A. Hanna, Y. Luo, Z. Wan, and S. S. Iyer, “Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric,” Proceedings of the IEEE Electronic Components and Technology Conference, pp. 579-586, May 2019.

U. Shah, U. Mogera, P. Ambore, B. Vaisband, S. S. Iyer, and T. S. Fisher, “Dynamic Thermal Management for Silicon Interconnect Fabric using Flash Cooling,” Proceedings of the IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, pp. 1228-1233, May 2019.

A. Bajwa, S. Jangam, S. Pal, B. Vaisband, R. Irwin, M. Goorsky, and S. S. Iyer, “Demonstration of a Heterogeneously Integrated System-on-Wafer (SoW) Assembly,” Proceedings of the IEEE Electronic Components and Technology Conference (ECTC), pp. 1926-1930, May 2018.

B. Vaisband, A. Bajwa, and S. S. Iyer, “Network on Interconnect Fabric,” Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), pp. 138-143, March 2018.

K. Xu, B. Vaisband, G. Sizikov, X. Li, and E. G. Friedman, “Distributed Sinusoidal Resonant Converter with High Step-Down Ratio,” Proceedings of the IEEE International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 1-3, October 2017.

B. Vaisband and E. G. Friedman, “Hybrid Energy Harvesting in 3-D IC IoT Devices,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2017.

B. Vaisband and E. G. Friedman, “3-D ICs as a Platform for IoT Devices,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2017.

B. Vaisband and E. G. Friedman, “Noise Coupling in TSV-Based Heterogeneous 3-D ICs,” Proceedings of the Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 2017.

B. Vaisband and E. G. Friedman, “Layer Ordering to Minimize TSVs in Heterogeneous 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1926-1929, May 2016.

B. Vaisband and E. G. Friedman, “3-D Floorplanning Algorithm to Minimize Thermal Interactions,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2133-2136, May 2015.

B. Vaisband, I. Savidis, and E. G. Friedman, “Thermal Conduction Path Analysis in 3-D ICs,” Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 594-597, June 2014.

B. Vaisband and E. G. Friedman, “Analysis of Thermal Paths in 3-D Structures,” Proceedings of the 37th Annual IEEE EDS/CAS Activities in Western New York Conference, p. 6, November 2013.